1. Field of Invention
The present invention relates to an active device array substrate and a display panel. More particularly, the present invention relates to an active device array substrate with a narrow frame area and a display panel.
2. Description of Related Art
The progressive development of display technology mainly dues to the advancement of the technology of electro-optical and semiconductor devices. Among the various display media, the liquid crystal display panel (LCD panel) provides the favorable features of reduced size and weight, low power consumption, free radiation, full color and portable, etc.; hence, the LCD panel becomes increasingly popular and the mainstream of display panels.
FIG. 1 is a schematic diagram of a conventional LCD panel. FIG. 2 is a partially enlarged view of region C of the LCD panel in FIG. 1. FIG. 2 illustrates the wiring of the active device arrange substrate of the LCD panel 100.
Referring concurrently to FIGS. 1 and 2, the LCD panel 100 includes a display region A and a peripheral circuit region B, wherein the display region A is configured with gate lines 120 and data lines 140. This LCD panel 100 adopts an integrated driver IC 170 for driving the gate lines 120 and the data lines 140. The gate lines 120 and the data lines 140 divide the display region A into a plurality of pixel regions D. A pixel electrode 150 and an active device 160 are configured in each pixel region D. Further, the common lines 132 that pass through the pixel region D provide storage capacitance to the pixel electrodes 150 for stabilizing the data voltage of the pixel electrodes 150. Moreover, the common lines 132 are connected to a Vcom bus line 130.
Additionally, multiple electronic devices and circuits, such as electric static discharge guard 110 (ESD guard), inspection switch device (not shown), Vcom bus line 130, etc., are disposed in the peripheral circuit region B. It is worthy to note that the gate lines 120 in the display region A extend to the peripheral circuit region B. The gate lines 120 extend to and arrange vertically in the peripheral circuit region B. In FIG. 2, only three vertically extending gate lines 120 are illustrated. However, it should be appreciate that a great part of the peripheral circuit region is occupied by a multiple of vertically extending gate lines 120.
Referring to FIG. 1, assuming the resolution of this LCD panel is 320 (V)×240 (H), each peripheral circuit region B at the right and left sides of the LCD panel 100 respectively accommodates at least 160 gate lines 120. More particularly, referring to FIG. 2, according to the LCD panel 100 array fabrication process and the fabrication capability of an exposure machine, if the line width “d” of the gate line 120 and the distance “w” between two gate lines 120 are both 4 micron (μm), the peripheral circuit region B at least requires to have a width of 0.004×2×160=1.28 millimeter (mm) to accommodate all these gate lines 120. If other ESD guards 110, Vcom bus lines 130 are to be included in the peripheral circuit region B, the width of the entire the peripheral circuit region B may exceed 2 millimeter (mm). As the resolution of the LCD panel 100 increases, the number of required gate lines 120 increases accordingly. Hence, more space is required in the peripheral circuit region B to accommodate these vertically arranged gate lines 120 and the multiple of electronic devices. Hence, the peripheral circuit region B of the LCD panel 100 can not be further reduced.
Further, although the common lines 132 are used to provide storage capacitor for the pixel electrodes 150, the stability of the storage capacitor is inadequate. Ultimately, the problems of flicker and cross talk are generated.